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Direct Transistor-Level Layout for Digital Blocks Prakash Gopalakrishnan Softcover reprint of the original 1st ed. 2004 edition
Direct Transistor-Level Layout for Digital Blocks
Prakash Gopalakrishnan
The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.
134 pages, 38 black & white illustrations, biography
| Mediji | Grāmatas Paperback Book (Grāmata ar mīksto vāku un līmēto muguru) |
| Izlaists | 2013. gada 23. marts |
| ISBN13 | 9781475779516 |
| Izdevēji | Springer-Verlag New York Inc. |
| Lapas | 125 |
| Izmēri | 155 × 235 × 8 mm · 204 g |
| Valoda | Angļu |
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