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Direct Transistor-Level Layout for Digital Blocks Prakash Gopalakrishnan 2004 edition
Direct Transistor-Level Layout for Digital Blocks
Prakash Gopalakrishnan
The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.
125 pages, 38 black & white illustrations, biography
| Mediji | Grāmatas Hardcover Book (Grāmata ar cieto muguriņu un vāku) |
| Izlaists | 2004. gada 17. jūnijs |
| ISBN13 | 9781402076657 |
| Izdevēji | Springer-Verlag New York Inc. |
| Lapas | 125 |
| Izmēri | 156 × 232 × 9 mm · 367 g |
| Valoda | Angļu |
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