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Advanced HDL Synthesis and SOC Prototyping Taraate 1st ed. 2019 edition
Advanced HDL Synthesis and SOC Prototyping
Taraate
This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs.
795 pages, 80 Illustrations, color; 60 Illustrations, black and white; V, 795 p. 140 illus., 80 illu
| Mediji | Grāmatas Book |
| Izlaists | 2019. gada 18. janvāris |
| ISBN13 | 9789811087752 |
| Izdevēji | Springer Verlag, Singapore |
| Lapas | 307 |
| Izmēri | 150 × 220 × 20 mm · 639 g |