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Jitter and Spur Minimization in Fractional-N Digital Frequency Synthesizers: Modeling, Simulation, Analysis, and Design Methodologies - Analog Circuits and Signal Processing Xu Wang
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Jitter and Spur Minimization in Fractional-N Digital Frequency Synthesizers: Modeling, Simulation, Analysis, and Design Methodologies - Analog Circuits and Signal Processing
Xu Wang
This book presents a rigorous and practically grounded treatment of jitter and spur minimization in fractional-N digital phase locked loops (DPLLs), addressing one of the most critical challenges in modern frequency synthesis.
| Mediji | Grāmatas Hardcover Book (Grāmata ar cieto muguriņu un vāku) |
| Izlaists | 2026. gada 13. augusts |
| ISBN13 | 9783032271853 |
| Izdevēji | Springer Nature Switzerland AG |
| Lapas | 226 |
| Izmēri | 150 × 220 × 20 mm · 578 g |
| Valoda | Vācu |
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