Pastāsti draugiem par šo preci:
Verification by Error Modeling: Using Testing Techniques in Hardware Verification - Frontiers in Electronic Testing Katarzyna Radecka 2003 edition
Verification by Error Modeling: Using Testing Techniques in Hardware Verification - Frontiers in Electronic Testing
Katarzyna Radecka
a
216 pages, biography
| Mediji | Grāmatas Hardcover Book (Grāmata ar cieto muguriņu un vāku) |
| Izlaists | 2003. gada 30. novembris |
| ISBN13 | 9781402076527 |
| Izdevēji | Springer-Verlag New York Inc. |
| Lapas | 216 |
| Izmēri | 155 × 235 × 14 mm · 548 g |
| Valoda | Angļu |