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Verilog HDL Design Examples Cavanagh, Joseph (Santa Clara University, California, USA) 1. izdevums
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Verilog HDL Design Examples
Cavanagh, Joseph (Santa Clara University, California, USA)
The book presents the Verilog language with a variety of examples to provide a firm foundation in the design of the digital system using Verilog HDL. It places emphasis on the detailed design of various Verilog projects that include the design module, test bench module, and outputs from the simulator illustrating the design's functional operation.
655 pages, 698 Line drawings, black and white; 34 Tables, black and white
| Mediji | Grāmatas Hardcover Book (Grāmata ar cieto muguriņu un vāku) |
| Izlaists | 2017. gada 13. oktobris |
| ISBN13 | 9781138099951 |
| Izdevēji | Taylor & Francis Ltd |
| Lapas | 674 |
| Izmēri | 260 × 184 × 44 mm · 1,40 kg |
| Valoda | Angļu |
