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Vhdl Modeling for Digital Design Synthesis Yu-chin Hsu 1995 edition
Vhdl Modeling for Digital Design Synthesis
Yu-chin Hsu
VHDL is a hardware description language that allows the specification of a digital system over different levels of abstraction. This text covers the synthesis aspects of VHDL, keeping the simulation specifics to a minimum.
356 pages, biography
| Mediji | Grāmatas Hardcover Book (Grāmata ar cieto muguriņu un vāku) |
| Izlaists | 1995. gada 31. jūlijs |
| ISBN13 | 9780792395973 |
| Izdevēji | Kluwer Academic Publishers |
| Lapas | 356 |
| Izmēri | 155 × 235 × 22 mm · 734 g |
| Valoda | Angļu |