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VHDL: A logic synthesis approach D. Naylor 1997 edition
VHDL: A logic synthesis approach
D. Naylor
This book is structured in a practical, example-driven, manner. The use of VHDL for constructing logic synthesisers is one of the aims of the book; the second is the application of the tools to the design process. An appendix on logic design the source code are available free of charge over the Internet.
340 pages, biography
| Mediji | Grāmatas Hardcover Book (Grāmata ar cieto muguriņu un vāku) |
| Izlaists | 1997. gada 31. jūlijs |
| ISBN13 | 9780412616501 |
| Izdevēji | Chapman and Hall |
| Lapas | 340 |
| Izmēri | 155 × 235 × 20 mm · 594 g |
| Valoda | Angļu |
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