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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip - Computer Architecture and Design Methodologies Zheng Wang Softcover reprint of the original 1st ed. 2018 edition
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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip - Computer Architecture and Design Methodologies
Zheng Wang
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors.
197 pages, 80 Tables, color; 72 Illustrations, color; 32 Illustrations, black and white; XX, 197 p.
| Mediji | Grāmatas Paperback Book (Grāmata ar mīksto vāku un līmēto muguru) |
| Izlaists | 2018. gada 12. maijs |
| ISBN13 | 9789811093210 |
| Izdevēji | Springer Verlag, Singapore |
| Lapas | 197 |
| Izmēri | 150 × 220 × 10 mm · 312 g |
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