Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling - Ayan Mandal - Grāmatas - Springer-Verlag New York Inc. - 9781493948178 - 2016. gada 23. augusts
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Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling Softcover reprint of the original 1st ed. 2014 edition

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This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.


156 pages, 85 black & white illustrations, 10 colour illustrations, 21 black & white tables, biograp

Mediji Grāmatas     Paperback Book   (Grāmata ar mīksto vāku un līmēto muguru)
Izlaists 2016. gada 23. augusts
ISBN13 9781493948178
Izdevēji Springer-Verlag New York Inc.
Lapas 143
Izmēri 155 × 235 × 9 mm   ·   231 g
Valoda Angļu  

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