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Loop Tiling for Parallelism - the Springer International Series in Engineering and Computer Science Jingling Xue 2000 edition
Loop Tiling for Parallelism - the Springer International Series in Engineering and Computer Science
Jingling Xue
Loop tiling, as one of the important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines.
256 pages, biography
| Mediji | Grāmatas Hardcover Book (Grāmata ar cieto muguriņu un vāku) |
| Izlaists | 2000. gada 31. augusts |
| ISBN13 | 9780792379331 |
| Izdevēji | Kluwer Academic Publishers |
| Lapas | 256 |
| Izmēri | 156 × 234 × 17 mm · 566 g |
| Valoda | Angļu |