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3D Integration for VLSI Systems
Three-dimensional (3D) integration is identified as a possible avenue for continuous performance growth in integrated circuits (IC) as the conventional scaling approach is faced with unprecedented challenges in fundamental and economic limits. Wafer level 3D IC can take several forms, and they usually include a stack of several thinned IC layers that are vertically bonded and interconnected by through silicon via TSV.
There is a long string of benefits that one can derive from 3D IC implementation such as form factor, density multiplication, improved delay and power, enhanced bandwidth, and heterogeneous integration. This book presents contributions by key researchers in this field, covering motivations, technology platforms, applications, and other design issues.
350 pages
| Mediji | Grāmatas Hardcover Book (Grāmata ar cieto muguriņu un vāku) |
| Izlaists | 2011. gada 26. septembris |
| ISBN13 | 9789814303811 |
| Izdevēji | Pan Stanford Publishing Pte Ltd |
| Lapas | 378 |
| Izmēri | 150 × 220 × 20 mm · 636 g |
| Valoda | Angļu |
| Redaktors | Chen, Kuan-Neng (National Chiao Tung University, Hsinchu, Taiwan) |
| Redaktors | Koester, Steven J. (IBM Research Division, Yorktown Heights, New York, USA) |
| Redaktors | Tan, Chuan Seng (Nanyang Technological University, Singapore) |
