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Post Silicon Validation and Debug 1st ed. 2019 edition
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Post Silicon Validation and Debug
This book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributions from SoC designers, academic researchers as well as SoC verification experts.
394 pages, 109 Tables, color; 113 Illustrations, color; 76 Illustrations, black and white; XV, 394 p
| Mediji | Grāmatas Book |
| Izlaists | 2018. gada 13. septembris |
| ISBN13 | 9783319981154 |
| Izdevēji | Springer International Publishing AG |
| Lapas | 394 |
| Izmēri | 160 × 242 × 31 mm · 781 g |
| Valoda | Vācu |
| Redaktors | Farahmandi, Farimah |
| Redaktors | Mishra, Prabhat |